(1)Field of the Invention
The present invention relates to an SOI (Silicon On Insulator) semiconductor device, and especially relates to a technology of improving the operating voltage of the SOI semiconductor device.
(2)Related Art
In order to electrically separate the semiconductor elements in a semiconductor integrated circuit, the dielectric isolation is often used. In the dielectric isolation, insulating layers are formed at the bottom and on the side of the semiconductor layer, which is the active layer of the semiconductor device. In this specification, this structure is referred to “dielectric isolation structure”.
The SOI semiconductor device with the dielectric isolation structure solves problems facing the conventional semiconductor device using the pn junction isolation, i.e., leakage current via the pn junction and unexpected bipolar effects. The SOI semiconductor device with the dielectric isolation structure is effectively used as the high voltage semiconductor device and the semiconductor device for analog switch.
The conventional SOI semiconductor device is disclosed in Japanese Patent Nos. 2896141 and 2878689.
Each of FIGS. 1 and 2 shows the structure of an n-type high voltage MOS (Metal Oxide Semiconductor) transistor as an example of the conventional SOI semiconductor device. An n-type high voltage MOS transistor 100 in FIG. 1 is manufactured as follows. A silicon dioxide film 102 is formed on a main surface of a semiconductor substrate 101, which is a supporting substrate of the SOI substrate. Then, an n−-type semiconductor layer 103, which is to be the active layer of the SOI substrate, overlies the silicon dioxide film 102. An isolation trench 104 extending to the silicon dioxide film 102 is formed on the n−-type semiconductor layer 103 by etching so as not to be affected by the potentials of the adjacent semiconductor elements. On the side walls of the isolation trench 104, silicon dioxide films 105 are formed. The isolation trench 104 is filled with polysilicon 106. As a result, the n−-type semiconductor layer 103 is electrically isolated from the other semiconductor island. More specifically, the n−-type semiconductor layer 103 is an island dielectrically isolated by the silicon dioxide films 102 and 105.
On the surface of the island n−-type semiconductor layer 103, gate oxide films 107, gate electrodes 108, a p-type semiconductor layer 109, a source electrode 112, n+-type semiconductor layers 110 and 111, and drain electrodes 113 are formed to form the n-type high voltage MOS transistor 100. The p-type semiconductor layer 109 is formed to form a channel region. The n+-type semiconductor layers 110 are connected to the source electrode 112 and surrounded by the p-type semiconductor layer 109. The n+-type semiconductor layers 111 are connected to the drain electrodes 113.
An n-type high voltage MOS transistors 150 in FIG. 2 has almost the same structure as the n-type high voltage MOS transistor 100 in FIG. 1. The n-type high voltage MOS transistor 150 is different from the n-type high voltage MOS transistor 100 in forming an n−-type semiconductor layer 114 between the n−-type semiconductor layer 103 and the silicon dioxide film 102 and forming an n+-type semiconductor layer 115 between the n−-type semiconductor layer 103 and the silicon dioxide film 105 so as to connect to the bottom of the n+-type semiconductor layers 111. Here, the impurity concentration is set as relatively low in the n−-type semiconductor layer 114 and the n+-type semiconductor layer 115. By doing so, a depletion layer is also formed around the n−-type semiconductor layer 114 and the n+-type semiconductor layer 115 in the n−-type semiconductor layer 103 so as to improve the operating.
Generally speaking, a voltage of 0V is applied to a semiconductor substrate 101 in the n-type high voltage MOS transistors 100 and 150 in FIGS. 1 and 2. When the potential of the p-type semiconductor layer 109 is almost the same as the potential of the semiconductor substrate 101, and a large and positive voltage is applied to the n+-type semiconductor layers 111, a pn junction diode consisting of the p-type semiconductor layer 109 and the n−-type semiconductor layer 103 is in a reverse bias state. In this case, a depletion layer extends from the interface between the p-type semiconductor layer 109 and the n−-type semiconductor layer 103. Due to the large and positive voltage applied to the n+-type semiconductor layers 111, the voltage of 0V applied to the semiconductor substrate 101, and the voltage applied to the p-type semiconductor layer 109, the depletion layer evenly extends in the n−-type semiconductor layer 103 to reduce the internal electric field.
As a result, avalanche breakdown hardly occurs in the n−-type semiconductor layer 103. The operating voltage of the n-type high voltage MOS transistor depends on the occurrence of the avalanche breakdown in the n−-type semiconductor layer 103. Accordingly, avalanche breakdown prevention can improve the operating voltage in the reverse bias state.
In the conventional SOI semiconductor device, however, especially, when the potential of the n+-type semiconductor layers 111 that are connected to the drain electrodes 113 is almost the same as the potential of the semiconductor substrate 101 as the supporting substrate of the SOI substrate, a depletion layer is not sufficiently formed in the n−-type semiconductor layer 103. As a result, the operating voltage in the reverse bias state, which mainly depends on the avalanche breakdown, conspicuously deteriorates.
More specifically, in the reverse bias state, in which a large and negative voltage is applied to the p-type semiconductor layer 109, a general voltage of 0V is applied to the semiconductor substrate 101, and a voltage of 0V is applied to the n+-type semiconductor layers 111, the semiconductor substrate 101 and the n+-type semiconductor layers 111 are at the same potential. This adversely affects the extension of the depletion layer. As a result, the depletion layer extending from the pn junction interface of the between the p-type semiconductor layer 109 and the n−-type semiconductor layer 103 does not sufficiently extend to reach regions of the n−-type semiconductor layer 103 under the n+-type semiconductor layers 111. Accordingly, the electric field strength arises in the n−-type semiconductor layer 103 and the avalanche breakdown tends to occur to drastically deteriorate the reverse bias voltage of the n-type MOS transistor.
As has been described, the operating voltage cannot be kept relatively high in any reverse bias state according to the conventional SOI semiconductor device structure. The avalanche breakdown tends to easily occur to deteriorate the operating voltage in a specific condition.